1. Field of the Invention
The present invention is related to a latch-up-free ESD protection circuit using an silicon controlled rectifier (SCR), and more particularly to an ESD protection circuit that employs a turn-on switch to turn on an SCR and a turn-off switch to switch off the SCR, whereby plural discharging paths are formed even after another part of the SCR is switched off.
2. Description of Related Art
When an operator touches a semiconductor device, the electrostatic charge stored on the surface of human body is transferred to the device with a burst of high voltage electrostatic charge, thus causing destructive damage to the device. Therefore, an ESD protection circuit is important to the reliable operation of any semiconductor device.
Two ESD protection schemes have been used. The first type of conventional ESD protection circuit employs a pair of gate-insulated MOSFET devices, and can be either a thick-oxide or a thin-oxide MOS device, and these MOSFET devices are connected to bipolar junction transistors. When electrostatic charge is present, the MOSFET devices are enabled and trigger the bipolar junction transistors (BJT) to form discharging paths. Once the electrostatic charge is removed, the MOSFET devices are turned off. One advantage of this ESD protection circuit is that latch-up will never occur, because the forward voltage will fall rapidly below a threshold voltage of the MOSFET device as the transient current flows through the circuit, but the efficiency in electrostatic discharge has not been satisfactory.
The second type of conventional ESD protection circuit, as shown in FIG. 7, uses a silicon controlled rectifier (SCR) (70) coupled by a resistor (71), to be placed across the negative power supply VSS, and the positive power supply VDD (or the input pad) where electrostatic discharge frequently occurs. When electrostatic charge builds up over the pad of the semiconductor device, breakdown current is produced to trigger the SCR (70) into conduction, such that a discharging path is created between the positive power supply VDD and the negative power supply VSS for ESD protection on the semiconductor device.
Compared with the previous example of the ESD protection circuit, the SCR (70) has better discharge efficiency. The ESD protection circuit using the SCR provides full ESD protection for semiconductor devices, but its problem is the high trigger voltage.
To correct the problem, many alternative ESD protection circuits are designed, such as a low voltage trigger LVTSCR shown in FIG. 8, a low voltage gate coupled GCSCR shown in FIG. 9, diode chain trigger DCTSCR shown in FIG. 10 and a Zener diode trigger ZDTSCR shown in FIG. 11. However, these circuits are not all without problems.
The ESD protection circuit, as shown in FIG. 9, is formed by low voltage trigger gate coupled SCR (GCSCR). Since the GCSCR only needs a low trigger voltage, the gate coupled SCR is enabled when overvoltage stress develops in the forward fast-transient mode, but this circuit needs to work with an RC circuit. Besides, the SCR will remain in latching after the transient current is stopped, and the circuit cannot tolerate high voltage DC.
The ESD protection circuit (DCTSCR), as shown in FIG. 10, is formed by a diode chain (D1–D4) triggered SCR, which is not only low voltage triggered, but also provides ESD protection in both fast-transient and quasi-static modes, but a more serious problem is the leakage current in forward bias.
ESD protection circuit (ZDTSCR), as shown in FIG. 11, employs a Zener diode triggered SCR. This circuit possesses the advantages of low voltage triggering, and ESD protection in both the fast-transient and quasi-static modes, and the only problem is that it takes longer time to be turned on.
The PMOS/NMOS triggered SCR ESD protection circuit, as shown in FIG. 12, employs a MOSFET circuit (81) to control the NPN transistor and the PNP transistor in the SCR circuit (82). When PMOS of the MOSFET circuit (81) is enabled, the NPN transistor of the SCR circuit (82) is turned on, so the SCR circuit (82) will be triggered into conduction for ESD protection. When NMOS of the MOSFET circuit (81) is enabled, the NPN transistor of the SCR circuit (82) is turned off, causing the SCR circuit (82) to be switched off. The advantage of this circuit design is fast triggering, and the SCR is immediately turned off when the transient current is stopped, but it only provides ESD protection in the fast-transient mode.
In conclusion, it can be seen that current designs of the ESD protection circuits still have many problems, such as leakage current, excessively high trigger voltage, low holding voltage, slow switching, low discharge efficiency, ESD protection only in fast-transient mode etc.